Stefan Michael Blawid

Patentes

2023

ARAUJO, GUILHERME JOSÉ FERREIRA DE; GOMES, A. S.

2023

ARAUJO, GUILHERME JOSÉ FERREIRA DE; GOMES, A. S.

2023

ARAUJO, GUILHERME JOSÉ FERREIRA DE; GOMES, A. S.

2023

ARAUJO, GUILHERME JOSÉ FERREIRA DE; GOMES, A. S.

2023

ARAUJO, GUILHERME JOSÉ FERREIRA DE; GOMES, A. S.

Patentes

2023

ARAUJO, GUILHERME JOSÉ FERREIRA DE; GOMES, A. S.

2023

ARAUJO, GUILHERME JOSÉ FERREIRA DE; GOMES, A. S.

2023

ARAUJO, GUILHERME JOSÉ FERREIRA DE; GOMES, A. S.

2023

ARAUJO, GUILHERME JOSÉ FERREIRA DE; GOMES, A. S.

2023

ARAUJO, GUILHERME JOSÉ FERREIRA DE; GOMES, A. S.

2023

ARAUJO, GUILHERME JOSÉ FERREIRA DE; GOMES, A. S.

2023

ARAUJO, GUILHERME JOSÉ FERREIRA DE; GOMES, A. S.

2023

ARAUJO, GUILHERME JOSÉ FERREIRA DE; GOMES, A. S.

2023

ARAUJO, GUILHERME JOSÉ FERREIRA DE; GOMES, A. S.

2023

ARAUJO, GUILHERME JOSÉ FERREIRA DE; GOMES, A. S.

Patentes

2007

Hard masking layer stack for use in semiconductor memory device, has carbon layer arranged on layer to be structured, and covering layer arranged on intermediate layer, where intermediate layer is thicker than covering layer

Manger, D.; Gutsch, M.; Lattard, L.; Roessiger, M.; Vogt, M.; Boubekeur, H.; Verhoeven, M.; Nagel, N.; Tatry, T.; Caspary, D.; Markert, M.; Bauch, L.; BLAWID, S; BLAWID, S.

País:Alemanha

Tipo:PRIVILEGIO DE INOVACAO PI

Categoria:Processo

Registro:DE102007012334

2007

Method of adjusting optical parameter of exposure apparatus involves optimizing optical model by adjusting one optical parameter so as to reduce overall difference between measured pattern data and simulated image

Pforr, R.; Winkler, T.; Ziebold, R.; Koestler, W.; Reichelt, J.; BLAWID, S; BLAWID, S.; Champigny, S.; Vorwerk, M.

País:Estados Unidos

Tipo:PRIVILEGIO DE INOVACAO PI

Categoria:Processo

Registro:US2008304029-A1

2007

Semiconductor device e.g. memory device provided with nitrided ROM memory cells, comprises carbon layer made of elemental carbon provided in contact on patterned layer, and cover layer formed on the top of carbon layer

Manger, D.; Gutsch, M.; Lattard, L.; Roessiger, M.; Vogt, M.; Boubekeur, H.; Verhoeven, M.; Nagel, N.; Tatry, T.; Caspary, D.; Markert, M.; Bauch, L.; BLAWID, S; BLAWID, S.

País:Estados Unidos

Tipo:PRIVILEGIO DE INOVACAO PI

Categoria:Processo

Registro:US2007243707-A1

2007

Semiconductor device including memory chips, flash memory chips, and microprocessors for electronic device, comprises structure comprising part of parallel linear structures and another structure comprising pad structures

BLAWID, S; BLAWID, S.; Lattard, L.; Knoefler, R.; Gutsch, M.; Pritchard, D.; Roessiger, M.

País:Estados Unidos

Tipo:PRIVILEGIO DE INOVACAO PI

Categoria:Processo

Registro:US2008261395-A1

2006

Hard mask layer stack for patterning target layer in manufacture of memory device, has predetermined layer of material, selected from group which comprises silicon oxide and silicon oxinitride that is arranged on top of carbon layer

Manger, D.; Lattard, L.; Roessiger, M.; Vogt, M.; Verhoeven, M.; Boubekeur, H.; Nagel, N.; Tatry, T.; Caspary, D.; Markert, M.; Bauch, L.; BLAWID, S.; BLAWID, S.; Gutsch, M.; et.al

País:Estados Unidos

Tipo:PRIVILEGIO DE INOVACAO PI

Categoria:Processo

Registro:US2007215986-A1

2006

Semiconductor device manufacture for making e.g. memory device involves patterning layer stack by performing lithographic exposures using different photomasks and arranging landing pads at side of array region defined by conductive lines

Lattard, L.; Roessiger, M.; Bauch, L.; BLAWID, S; BLAWID, S.; Gutsch, M.

País:Estados Unidos

Tipo:PRIVILEGIO DE INOVACAO PI

Categoria:Processo

Registro:US2007218627-A1

2006

Termination structure for manufacturing e.g. dynamic RAM-chip, has extension element adjacent to line-shaped element, where longest axis of line-shaped element is three times higher than broadest width of line-shaped element

BLAWID, S; BLAWID, S.; Koestler, W.; Ziebold, R.

País:Estados Unidos

Tipo:PRIVILEGIO DE INOVACAO PI

Categoria:Processo

Registro:US2008028359-A1

2006

Semiconductor device manufacturing method, involves providing semiconductor substrate available with surface, and layer pile comprising conductive layer on substrate surface

Lattard, L.; Roessiger, M.; Bauch, L.; BLAWID, S; BLAWID, S.; Gutsch, M.

País:Alemanha

Tipo:PRIVILEGIO DE INOVACAO PI

Categoria:Processo

Registro:DE102006024741

2023

ARAUJO, GUILHERME JOSÉ FERREIRA DE; GOMES, A. S.

2023

ARAUJO, GUILHERME JOSÉ FERREIRA DE; GOMES, A. S.

2023

ARAUJO, GUILHERME JOSÉ FERREIRA DE; GOMES, A. S.

2023

ARAUJO, GUILHERME JOSÉ FERREIRA DE; GOMES, A. S.

2023

ARAUJO, GUILHERME JOSÉ FERREIRA DE; GOMES, A. S.

Patentes

2007

Hard masking layer stack for use in semiconductor memory device, has carbon layer arranged on layer to be structured, and covering layer arranged on intermediate layer, where intermediate layer is thicker than covering layer

Manger, D.; Gutsch, M.; Lattard, L.; Roessiger, M.; Vogt, M.; Boubekeur, H.; Verhoeven, M.; Nagel, N.; Tatry, T.; Caspary, D.; Markert, M.; Bauch, L.; BLAWID, S; BLAWID, S.

País:Alemanha

Tipo:PRIVILEGIO DE INOVACAO PI

Categoria:Processo

Registro:DE102007012334

2007

Method of adjusting optical parameter of exposure apparatus involves optimizing optical model by adjusting one optical parameter so as to reduce overall difference between measured pattern data and simulated image

Pforr, R.; Winkler, T.; Ziebold, R.; Koestler, W.; Reichelt, J.; BLAWID, S; BLAWID, S.; Champigny, S.; Vorwerk, M.

País:Estados Unidos

Tipo:PRIVILEGIO DE INOVACAO PI

Categoria:Processo

Registro:US2008304029-A1

2007

Semiconductor device e.g. memory device provided with nitrided ROM memory cells, comprises carbon layer made of elemental carbon provided in contact on patterned layer, and cover layer formed on the top of carbon layer

Manger, D.; Gutsch, M.; Lattard, L.; Roessiger, M.; Vogt, M.; Boubekeur, H.; Verhoeven, M.; Nagel, N.; Tatry, T.; Caspary, D.; Markert, M.; Bauch, L.; BLAWID, S; BLAWID, S.

País:Estados Unidos

Tipo:PRIVILEGIO DE INOVACAO PI

Categoria:Processo

Registro:US2007243707-A1

2007

Semiconductor device including memory chips, flash memory chips, and microprocessors for electronic device, comprises structure comprising part of parallel linear structures and another structure comprising pad structures

BLAWID, S; BLAWID, S.; Lattard, L.; Knoefler, R.; Gutsch, M.; Pritchard, D.; Roessiger, M.

País:Estados Unidos

Tipo:PRIVILEGIO DE INOVACAO PI

Categoria:Processo

Registro:US2008261395-A1

2006

Hard mask layer stack for patterning target layer in manufacture of memory device, has predetermined layer of material, selected from group which comprises silicon oxide and silicon oxinitride that is arranged on top of carbon layer

Manger, D.; Lattard, L.; Roessiger, M.; Vogt, M.; Verhoeven, M.; Boubekeur, H.; Nagel, N.; Tatry, T.; Caspary, D.; Markert, M.; Bauch, L.; BLAWID, S.; BLAWID, S.; Gutsch, M.; et.al

País:Estados Unidos

Tipo:PRIVILEGIO DE INOVACAO PI

Categoria:Processo

Registro:US2007215986-A1

2006

Semiconductor device manufacture for making e.g. memory device involves patterning layer stack by performing lithographic exposures using different photomasks and arranging landing pads at side of array region defined by conductive lines

Lattard, L.; Roessiger, M.; Bauch, L.; BLAWID, S; BLAWID, S.; Gutsch, M.

País:Estados Unidos

Tipo:PRIVILEGIO DE INOVACAO PI

Categoria:Processo

Registro:US2007218627-A1

2006

Termination structure for manufacturing e.g. dynamic RAM-chip, has extension element adjacent to line-shaped element, where longest axis of line-shaped element is three times higher than broadest width of line-shaped element

BLAWID, S; BLAWID, S.; Koestler, W.; Ziebold, R.

País:Estados Unidos

Tipo:PRIVILEGIO DE INOVACAO PI

Categoria:Processo

Registro:US2008028359-A1

2006

Semiconductor device manufacturing method, involves providing semiconductor substrate available with surface, and layer pile comprising conductive layer on substrate surface

Lattard, L.; Roessiger, M.; Bauch, L.; BLAWID, S; BLAWID, S.; Gutsch, M.

País:Alemanha

Tipo:PRIVILEGIO DE INOVACAO PI

Categoria:Processo

Registro:DE102006024741

2023

ARAUJO, GUILHERME JOSÉ FERREIRA DE; GOMES, A. S.

2023

ARAUJO, GUILHERME JOSÉ FERREIRA DE; GOMES, A. S.

2023

ARAUJO, GUILHERME JOSÉ FERREIRA DE; GOMES, A. S.

2023

ARAUJO, GUILHERME JOSÉ FERREIRA DE; GOMES, A. S.

2023

ARAUJO, GUILHERME JOSÉ FERREIRA DE; GOMES, A. S.

sblawid

Stefan Michael Blawid

Professor Adjunto III

Processamento e Sintese de midias digitais

Design Thinking

Link para o perfil do sigaa de Stefan Michael Blawid

E-mail

sblawid@cin.ufpe.br

Telefone

+55 81 2126-8430 R:4328

Sala

B209

sblawid

Stefan Michael Blawid

Professor Adjunto III

Processamento e Sintese de midias digitais

Design Thinking

E-mail

sblawid@cin.ufpe.br

Telefone

+55 81 2126-8430 R:4328

Sala

B209

2007

Hard masking layer stack for use in semiconductor memory device, has carbon layer arranged on layer to be structured, and covering layer arranged on intermediate layer, where intermediate layer is thicker than covering layer

Manger, D.; Gutsch, M.; Lattard, L.; Roessiger, M.; Vogt, M.; Boubekeur, H.; Verhoeven, M.; Nagel, N.; Tatry, T.; Caspary, D.; Markert, M.; Bauch, L.; BLAWID, S; BLAWID, S.

País:Alemanha

Tipo:PRIVILEGIO DE INOVACAO PI

Categoria:Processo

Registro:DE102007012334

2007

Method of adjusting optical parameter of exposure apparatus involves optimizing optical model by adjusting one optical parameter so as to reduce overall difference between measured pattern data and simulated image

Pforr, R.; Winkler, T.; Ziebold, R.; Koestler, W.; Reichelt, J.; BLAWID, S; BLAWID, S.; Champigny, S.; Vorwerk, M.

País:Estados Unidos

Tipo:PRIVILEGIO DE INOVACAO PI

Categoria:Processo

Registro:US2008304029-A1

2007

Semiconductor device e.g. memory device provided with nitrided ROM memory cells, comprises carbon layer made of elemental carbon provided in contact on patterned layer, and cover layer formed on the top of carbon layer

Manger, D.; Gutsch, M.; Lattard, L.; Roessiger, M.; Vogt, M.; Boubekeur, H.; Verhoeven, M.; Nagel, N.; Tatry, T.; Caspary, D.; Markert, M.; Bauch, L.; BLAWID, S; BLAWID, S.

País:Estados Unidos

Tipo:PRIVILEGIO DE INOVACAO PI

Categoria:Processo

Registro:US2007243707-A1

2007

Semiconductor device including memory chips, flash memory chips, and microprocessors for electronic device, comprises structure comprising part of parallel linear structures and another structure comprising pad structures

BLAWID, S; BLAWID, S.; Lattard, L.; Knoefler, R.; Gutsch, M.; Pritchard, D.; Roessiger, M.

País:Estados Unidos

Tipo:PRIVILEGIO DE INOVACAO PI

Categoria:Processo

Registro:US2008261395-A1

2006

Hard mask layer stack for patterning target layer in manufacture of memory device, has predetermined layer of material, selected from group which comprises silicon oxide and silicon oxinitride that is arranged on top of carbon layer

Manger, D.; Lattard, L.; Roessiger, M.; Vogt, M.; Verhoeven, M.; Boubekeur, H.; Nagel, N.; Tatry, T.; Caspary, D.; Markert, M.; Bauch, L.; BLAWID, S.; BLAWID, S.; Gutsch, M.; et.al

País:Estados Unidos

Tipo:PRIVILEGIO DE INOVACAO PI

Categoria:Processo

Registro:US2007215986-A1

2006

Semiconductor device manufacture for making e.g. memory device involves patterning layer stack by performing lithographic exposures using different photomasks and arranging landing pads at side of array region defined by conductive lines

Lattard, L.; Roessiger, M.; Bauch, L.; BLAWID, S; BLAWID, S.; Gutsch, M.

País:Estados Unidos

Tipo:PRIVILEGIO DE INOVACAO PI

Categoria:Processo

Registro:US2007218627-A1

2006

Termination structure for manufacturing e.g. dynamic RAM-chip, has extension element adjacent to line-shaped element, where longest axis of line-shaped element is three times higher than broadest width of line-shaped element

BLAWID, S; BLAWID, S.; Koestler, W.; Ziebold, R.

País:Estados Unidos

Tipo:PRIVILEGIO DE INOVACAO PI

Categoria:Processo

Registro:US2008028359-A1

2006

Semiconductor device manufacturing method, involves providing semiconductor substrate available with surface, and layer pile comprising conductive layer on substrate surface

Lattard, L.; Roessiger, M.; Bauch, L.; BLAWID, S; BLAWID, S.; Gutsch, M.

País:Alemanha

Tipo:PRIVILEGIO DE INOVACAO PI

Categoria:Processo

Registro:DE102006024741

2007

Hard masking layer stack for use in semiconductor memory device, has carbon layer arranged on layer to be structured, and covering layer arranged on intermediate layer, where intermediate layer is thicker than covering layer

Manger, D.; Gutsch, M.; Lattard, L.; Roessiger, M.; Vogt, M.; Boubekeur, H.; Verhoeven, M.; Nagel, N.; Tatry, T.; Caspary, D.; Markert, M.; Bauch, L.; BLAWID, S; BLAWID, S.

País:Alemanha

Tipo:PRIVILEGIO DE INOVACAO PI

Categoria:Processo

Registro:DE102007012334

2007

Method of adjusting optical parameter of exposure apparatus involves optimizing optical model by adjusting one optical parameter so as to reduce overall difference between measured pattern data and simulated image

Pforr, R.; Winkler, T.; Ziebold, R.; Koestler, W.; Reichelt, J.; BLAWID, S; BLAWID, S.; Champigny, S.; Vorwerk, M.

País:Estados Unidos

Tipo:PRIVILEGIO DE INOVACAO PI

Categoria:Processo

Registro:US2008304029-A1

2007

Semiconductor device e.g. memory device provided with nitrided ROM memory cells, comprises carbon layer made of elemental carbon provided in contact on patterned layer, and cover layer formed on the top of carbon layer

Manger, D.; Gutsch, M.; Lattard, L.; Roessiger, M.; Vogt, M.; Boubekeur, H.; Verhoeven, M.; Nagel, N.; Tatry, T.; Caspary, D.; Markert, M.; Bauch, L.; BLAWID, S; BLAWID, S.

País:Estados Unidos

Tipo:PRIVILEGIO DE INOVACAO PI

Categoria:Processo

Registro:US2007243707-A1

2007

Semiconductor device including memory chips, flash memory chips, and microprocessors for electronic device, comprises structure comprising part of parallel linear structures and another structure comprising pad structures

BLAWID, S; BLAWID, S.; Lattard, L.; Knoefler, R.; Gutsch, M.; Pritchard, D.; Roessiger, M.

País:Estados Unidos

Tipo:PRIVILEGIO DE INOVACAO PI

Categoria:Processo

Registro:US2008261395-A1

2006

Hard mask layer stack for patterning target layer in manufacture of memory device, has predetermined layer of material, selected from group which comprises silicon oxide and silicon oxinitride that is arranged on top of carbon layer

Manger, D.; Lattard, L.; Roessiger, M.; Vogt, M.; Verhoeven, M.; Boubekeur, H.; Nagel, N.; Tatry, T.; Caspary, D.; Markert, M.; Bauch, L.; BLAWID, S.; BLAWID, S.; Gutsch, M.; et.al

País:Estados Unidos

Tipo:PRIVILEGIO DE INOVACAO PI

Categoria:Processo

Registro:US2007215986-A1

2006

Semiconductor device manufacture for making e.g. memory device involves patterning layer stack by performing lithographic exposures using different photomasks and arranging landing pads at side of array region defined by conductive lines

Lattard, L.; Roessiger, M.; Bauch, L.; BLAWID, S; BLAWID, S.; Gutsch, M.

País:Estados Unidos

Tipo:PRIVILEGIO DE INOVACAO PI

Categoria:Processo

Registro:US2007218627-A1

2006

Termination structure for manufacturing e.g. dynamic RAM-chip, has extension element adjacent to line-shaped element, where longest axis of line-shaped element is three times higher than broadest width of line-shaped element

BLAWID, S; BLAWID, S.; Koestler, W.; Ziebold, R.

País:Estados Unidos

Tipo:PRIVILEGIO DE INOVACAO PI

Categoria:Processo

Registro:US2008028359-A1

2006

Semiconductor device manufacturing method, involves providing semiconductor substrate available with surface, and layer pile comprising conductive layer on substrate surface

Lattard, L.; Roessiger, M.; Bauch, L.; BLAWID, S; BLAWID, S.; Gutsch, M.

País:Alemanha

Tipo:PRIVILEGIO DE INOVACAO PI

Categoria:Processo

Registro:DE102006024741